Method for automatically detecting the clock frequency of a system clock pulse for the configuration of a peripheral device

ABSTRACT

The present invention provides a method for automatic identification of the clock frequency of a system clock ( 15 ) for the configuration of a peripheral device ( 12 ), having the following steps: generation of a secondary clock ( 16 ) at a predetermined clock frequency; application of the system clock ( 15 ) and of the secondary clock ( 16 ) to a host ( 10 ); application of the system clock ( 15 ) and of the secondary clock ( 16 ) to the peripheral device ( 12 ); determination of the clock frequency of the system clock ( 15 ) in the peripheral device ( 12 ) by means of the secondary clock ( 16 ); and configuration of the peripheral device ( 12 ) using the determined system clock ( 15 ).

FIELD OF THE INVENTION

The present invention relates to a method for automatic identificationof the clock frequency of a system clock for the configuration of aperipheral device, and in particular to a method for automaticidentification of the clock frequency of a system clock for theconfiguration of a mobile radio peripheral device.

BACKGROUND

In the course of the increasing integration of widely differingcomponents in an appliance, it appears to be worthwhile to make use ofthe components which are already present in an appliance, and/or theresources of different components, that is to say more than once. Thus,for example, particularly in the mobile radio sector, it is possible tointegrate a peripheral device, such as a Bluetooth module, in a GSM,CDMA cellular telephone, as a host device or host. The peripheral deviceor module should in this case use the same system clock, typically forexample 10-100 MHz, as the main device or the host device.

FIG. 3 shows, schematically, a known arrangement for implementation ofdata interchange 14 between a first interface 11 of a host 10, and asecond interface 13 of a peripheral module or of a peripheral device 12,as a function of a system clock 15. The main device 10 or the host andthe peripheral module 12 in this case each interchange data 14 via aninterface 11, 13. In order to allow the system costs to be reduced andin order to allow multiple use, both the host 10 and the module 12 areable to process and to cover a certain frequency range of system clocks15 and their frequencies.

In order to make is possible to ensure this, it is necessary toconfigure both the host 10 and the peripheral module 12 to the systemclock 15. One possible known arrangement is shown in FIG. 2, as anexample of the peripheral module 12. The system clock 15 is supplied tothe peripheral device 12 and is processed by a PLL (phase locked loop)17, using a constant clock 18, which in turn is supplied to an interface13 and/or to a processing device 19, for example a processor, acontroller or a memory.

In order now, by way of example, to achieve a cost reduction for theoverall system, the system is designed such that only the host 10 knowsthe precise system clock, and/or the host 10 can vary the clock duringoperation and must then signal this to the module 12. The module 12therefore has no separate memory or the like containing any informationabout the system clock. The interface 13 of the module 12 must beconfigured to a specific transmission rate, typically, for example, 10kbaud to 10 Mbaud, in which case this interface transmission rate mustbe within a specific tolerance band both for the main device 10 and forthe peripheral module 12, with this tolerance band being defined, forexample, by an interface standard. In this case, the actual transmissionrate is dependent on the system clock 15, when the clock for supplyingthe individual internal components 13, 17, 19 of the peripheral device12 is derived from the system clock 15 and, in consequence, inproportion to it.

In the known arrangement shown in FIG. 3, the information about thesystem clock 15 can be signaled to the module 12 in such a way that, inthe initialization phase, all of the internal components 13, 17, 19 ofthe module 12 are supplied with the system clock 15 or withpredetermined clock ratios of this clock. This precondition must beensured by the module 12 both in terms of hardware and software in apredetermined minimum/maximum range of the system clock 15. Thetransmission rate of the interface 13 is then chosen as a fixed ratio tothe system clock 15, thus ensuring that the main device 10 and theperipheral device 12 have the same transmission rate at the interfaces11, 13, and can thus communicate with one another. The information aboutthe system clock, and likewise about the desired transmission rate forthe interfaces 11, 13, is then signaled to the module 12 via thisinterface 13. The host 10 can then switch the interface transmissionrate once the module has been configured to the known system clock 15and the interface transmission rate has been set.

Complex configuration of the peripheral module to the system clock musttherefore be carried out. Furthermore, the known system implementationis based on the principle that the transmission rate of the interfacemust be set as a fixed ratio to the system clock in the initializationphase, in order that the host and the module provide the sametransmission rate at their interfaces.

SUMMARY

The object of the present invention is thus to provide a method forautomatic identification of the clock frequency of a system clock forthe configuration of a peripheral device, by means of which the processof configuration of the peripheral device is simplified.

According to the invention, this object is achieved by the method forautomatic identification of the clock frequency of a system clock forthe configuration of a peripheral device.

The idea on which the present invention is based is essentially toprovide both the main device and the peripheral device with a furtherclock signal at a precisely known clock frequency, which further clocksignal is used, for example, for low-power modes, such as a 32.768 kHzclock signal.

In the present invention, the problem mentioned initially is solved inparticular by providing a method for automatic identification of theclock frequency of a system clock for the configuration of a peripheraldevice having the following steps: generation of a secondary clock at apredetermined clock frequency; application of the system clock and of asecondary clock to a host; application of the system clock and of thesecondary clock to the peripheral device; determination of the clockfrequency of the system clock in the peripheral device by means of thesecondary clock; and configuration of the peripheral device using thedetermined system clock.

Advantageous developments and improvements of the subject matter of theinvention can be found in the dependent claims.

According to one preferred development, the system clock is determinedby counting a number of edge changes of the system clock within apredetermined number of periods of the secondary clock.

According to a further preferred development, during the configurationof the peripheral device, the identical interface transmission rate isset for the first and second interface as a function of the determinedsystem clock.

According to a further preferred development, the interface transmissionrate is set to an interface transmission rate which is defined by thestandard of the interfaces.

According to a further preferred development, after an initializationphase, the system clock can be changed by the main device with a systemclock (which is then new) of the peripheral device being signaledexactly via the interfaces.

According to a further preferred development, tolerances of both thesystem clock and of the secondary clock are taken into account in thedetermination of the system clock by the peripheral device.

According to a further preferred development, the transmission rate ofthe data transmission between the first interface and the secondinterface is dependent on the system clock.

According to a further preferred development, the clock frequency of thesystem clock is variable at predetermined clock frequencies and isdetermined by the main device after an initialization phase.

According to a further preferred development, the clock frequency of thesystem clock, which is determined automatically by the peripheraldevice, has discrete clock frequencies which are compared in theperipheral device with discrete clock frequencies that are stored in atable, in order to use the tabular value of the clock frequency as thecurrent clock frequency of the system clock.

According to a further preferred development, a PLL circuit in theperipheral device generates a constant clock frequency from the systemclock frequency, which clock frequency is supplied to the secondinterface and/or to a processing device, such as a processor, controlleror memory.

One exemplary embodiment of the invention is illustrated in the drawingsand will be explained in more detail in the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

In the figure:

FIG. 1 shows a schematic block diagram in order to explain oneembodiment of the present invention;

FIG. 2 shows a schematic block diagram of one known peripheral device;and

FIG. 3 shows a schematic block diagram of a conventional arrangement.

DETAILED DESCRIPTION

Identical reference symbols in the figures denote identical orfunctionally identical components.

FIG. 1 shows an arrangement for automatic determination of the clockfrequency of a system clock according to one embodiment of the presentinvention. The arrangement shown in FIG. 1 has a main device 10 or ahost, which has a first interface 11. A peripheral device 12 is alsoprovided, and likewise has an interface 13. The aim is for datainterchange 14 to be possible between the first interface 11 of the maindevice 10 and the second interface 13 of the peripheral device or of theperipheral module. Both the host device 10 and the peripheral module 12are supplied with a system clock 15. Furthermore, both the peripheralmodule 12 and the host device 10 are supplied with a secondary clocksignal 16. The peripheral module 12 preferably has a structure asdescribed with reference to FIG. 2.

First of all, a secondary clock 16 is produced at a specific known clockfrequency, for example a crystal clock frequency. The peripheral device12 or the module can then use its knowledge of the clock frequency ofthe secondary clock 16 to itself determine the clock frequency of thesystem clock 15 that is likewise present, for example by measuring, thatis to say in particular by counting, the number of edge changes orrising or falling edges of the system clock 15 within one or moreperiods of the secondary clock 16, or of the low-power clock. Thetolerances of both the clock frequency of the system clock 15 and theclock frequency of the secondary clock 16 must be taken into account inthis case, and their influence on the determined clock frequency of thesystem clock 15 may be minimized, for example by a number ofmeasurements.

If mapping onto exact system clock frequencies is not intended, then theclock frequency of the system clock as determined automatically by theperipheral device 12, including any possible error resulting frompossible tolerances of the system clock 15 and of the secondary clock 16that are supplied may be used. This automatically determined clockfrequency of the system clock is then used to set the interface 13 inthe peripheral device 12 to an interface transmission rate as defined bythe interface standard, for example RS232. Since the tolerances in theinterface transmission rate as accepted by the first and secondinterfaces 11, 13 of the main and peripheral devices 10, 12 are ingeneral considerably wider than the tolerances which can be expected inthe system clock 15 and in the secondary clock 16, communication cannevertheless take place between the host 10 and the module 12.Subsequently, the main device 10 can then signal to the peripheralmodule 12 the exact system clock via the data interchange 14 which iscarried out via the interfaces 11, 13.

Since, in general, the system clock 15 does not have undefined clockrates or frequency values, but, in general, only predetermined discreteclock rates or possible frequency values occur, these may be stored, forexample, in a table in the peripheral device 12, and are then comparedwith the clock frequency of the clock signal 15 as determinedautomatically by the peripheral device 12. The closest tabular value toa clock frequency of the system clock rate in the peripheral device 12can then be used on the basis of this comparison, thus allowing anassociation with an exact clock frequency of the system clock even inthe event of possible tolerances of the clock frequency of the systemclock 15 and/or of the secondary clock 16.

In consequence, with the method according to the invention, there is noneed to carry out a basic configuration of the module for the clockfrequency of the system clock 15 but the setting of a differentinterface transmission rate to the preset interface transmission ratebetween the interfaces 11 and 13 of the host 10 and of the peripheraldevice 12, respectively, remains, with this setting in general beingstandardized. Furthermore, with the described method, it is notessential for the transmission rate of the interface to be set in aninitialization phase as a fixed ratio to the clock frequency of thesystem clock, but, according to the invention, once the clock frequencyof the system clock 15 has been determined automatically, datainterchange 14 can take place at an interface transmission rate asdefined by the interface standard, thus allowing communication betweenthe host 10 and the peripheral device 12.

Although the present invention has been described above with referenceto a mobile radio device, it is not restricted to this but, inprinciple, can be extended to any desired system with a host and aperipheral device between which communication is intended to take place.Furthermore, the method for determination of the system clock can beseen, by way of example, in the counting of the edge changes, risingedges or falling edges of the system clock within one or more periods ofthe secondary clock, and may also be carried out in a different manner.In particular, the peripheral device (12) may, for example, be aBluetooth module and may be configured for the system clock of a mobileradio device, for example a cellular telephone.

LIST OF REFERENCE SYMBOLS

-   10 Main device, host-   11 Interface of the main device (data interchange)-   12 Peripheral device, peripheral module-   13 Interface of the peripheral device-   14 Data interchange-   15 System clock-   16 Secondary clock, for example a low-power clock; 32.768 kHz clock-   17 PLL (phase locked loop)-   18 Constant clock-   19 Processing devices, for example processor, controller, memory

1. A method of identifying a clock frequency of a system clock for theconfiguration of a peripheral device, the method comprising: a)providing a secondary clock at a predetermined clock frequency; b)applying the system clock and the secondary clock to a host; c) applyingthe system clock and the secondary clock to the peripheral device; d)determining the clock frequency of the system clock in the peripheraldevice using the second clock and based on the predetermined clockfrequency; and e) configuring the peripheral device using the determinedsystem clock; wherein the clock frequency of the system clock isvariable at predetermined clock frequencies and further comprising astep of employing the host to determine the clock frequency after aninitialization phase; and wherein step d) further comprises determiningthe clock frequency with a tolerance in the peripheral device, and thencomparing, in the peripheral device, the determined clock frequency withthe tolerance to a table of possible frequency values and selecting inthe peripheral device the clock frequency of the system clock based onthe comparison.
 2. The method as claimed in claim 1, wherein step d)further comprises counting a number of edge changes of the system clockwithin a predetermined number of periods of the secondary clock.
 3. Themethod as claimed in claim 2, wherein step e) further comprises settingan identical interface transmission rate for a first interface of thehost and for a second interface of the peripheral device as a functionof the clock frequency of the determined system clock.
 4. The method asclaimed in claim 3, wherein step e) further comprises setting theinterface transmission rate to an interface transmission rate defined bya predetermined standard.
 5. The method as claimed in claim 3, whereinfurther comprising: after an initialization phase, employing the host tochange the system clock; and signaling information representative of thechange to the peripheral device through the second interface.
 6. Themethod as claimed in claim 1, wherein step d) further comprisesemploying tolerances of both the system clock and the second clock todetermine the clock frequency of the system clock in the peripheraldevice.
 7. The method as claimed in claim 1, wherein a transmission rateof data transmission between a first interface of the host and a secondinterface of the peripheral device is dependent on the clock frequencyof the system clock.
 8. The method as claimed in claim 1, furthercomprising employing a PLL circuit in the peripheral device to generatea constant clock frequency from the clock frequency of the system clock.9. The method as claimed in one of the preceding claims, furthercomprising providing a Bluetooth module as the peripheral device, theBluetooth module configured for the system clock of a mobile radiodevice.
 10. A method of identifying a clock frequency of a system clockfor the configuration of a peripheral device, the method comprising: a)providing a secondary clock at a predetermined clock frequency; b)applying the system clock and the secondary clock to a host; c) applyingthe system clock and the secondary clock to the peripheral device; d)determining the clock frequency of the system clock in the peripheraldevice using the second clock based on the predetermined clockfrequency; and e) setting an identical interface transmission rate for afirst interface of the host and for a second interface of the peripheraldevice as a function of the clock frequency of the determined systemclock; wherein step d) further comprises determining the clock frequencywith a tolerance in the peripheral device, and then comparing, in theperipheral device, the determined clock frequency with the tolerance toa table of possible frequency values and selecting in the peripheraldevice the clock frequency of the system clock based on the comparison.11. The method as claimed in claim 10, wherein step d) further comprisescounting a number of edge changes of the system clock within apredetermined number of periods of the secondary clock.
 12. The methodas claimed in claim 11, wherein step e) further comprises setting theinterface transmission rate to an interface transmission rate defined bya predetermined standard.
 13. The method as claimed in claim 11, whereinfurther comprising: after an initialization phase, employing the host tochange the system clock; and signaling information representative of thechange to the peripheral device through the second interface.
 14. Themethod as claimed in claim 10, wherein step d) further comprisesemploying tolerances of both the system clock and the second clock todetermine the clock frequency of the system clock in the peripheraldevice.
 15. The method as claimed in claim 10, wherein a transmissionrate of data transmission between a first interface of the host and asecond interface of the peripheral device is dependent on the clockfrequency of the system clock.
 16. The method as claimed in claim 10,wherein the clock frequency of the system clock is variable atpredetermined clock frequencies and further comprising a step ofemploying the host to determine the clock frequency after aninitialization phase.